QG80331M667 datasheet(47/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Specification Changes

HPI# (High Priority Interrupt) is a maskable interrupt

Issue:

The HPI# interrupt input is both maskable and masked by default (as are all interrupts). It is

controlled by INTCTL1.31. HPI# operates the same as the other external interrupt inputs

(S_INT[D:A]#).

PCIODT_EN Reset Strap Signal

Issue:

PCI Bus ODT Enable (PCIODT_EN) is a reset strap muxed onto signal A[20] and is latched on the

rising (de-asserting) edge of P_RST#. It is used to determine when the secondary PCI(-X) bus uses

internal pull-ups on the following signals:

S_AD[63:32], S_C/BE[7:4]#, S_PAR64, S_REQ64#, S_REQ[3:0]#, S_ACK64#,

S_FRAME#, S_IRDY#, S_DEVSEL#, S_TRDY#, S_STOP#, S_PERR#, S_LOCK#,

S_M66EN, S_SERR# and S_INT[D:A]#.

When disabled, then external pull-up resistors are required. PCI ODT enable is valid for the 80331

secondary PCI bus only.

Secondary PCI bus options:

1. PCIODTEN = 1 (default), enables 8.2 K internal pull-ups to 3.3 V.

2. PCIODTEN = 0, external 8.2 K pull-ups to 3.3 V are required.

LOCK# functionality has been de-featured

Issue:

The LOCK# functionality of the PCI-X bridge has been de-featured from the 80331.

Watchdog Timer and Retry Timer has been de-featured

Issue:

The Watchdog Timer and Retry Timer of the PCI-X bridge has been de-featured from the 80331.

P_GNT# and P_REQ# signals have new ball locations on B-0

Issue:

The location of P_REQ# and P_GNT# on A-1 causes a violation of the maximum trace length

required by the PCI Local Bus Specification, Revision 2.3:

P_REQ# signal is moving from T6 on A-1 to H11 on B-0.

P_GNT# signal is moving from R4 on A-1 to G12 on B-0.

The 80331 boards need to incorporate series resistors that can be populated/de-populated for

connection to either the A-1 or B-0 P_REQ#/P_GNT# ball location. Route the P_REQ# net to the

two ball locations as separate routes through two 0 ohm series resistor located near the PCI edge

connector. Route the P_GNT# net to the two ball locations as separate routes through two 0 ohm

series resistor located near the PCI edge connector. Populate the resistor that connects the net to the

correct ball according to the silicon revision.

Peripheral Performance Monitor Unit has been de-featured

Issue:

The Peripheral Performance Monitor Unit has been de-featured. The Intel XScale® core PMON is

still functional.

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