STLC5466 datasheet(65/130 Pages) STMICROELECTRONICS

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STLC5466

READ : READ COMMAND MEMORY

READ = 1, READ COMMAND MEMORY.

READ = 0, WRITE COMMAND MEMORY.

CH0/4 : These five bits define one of 32 channels of the second 32 HDLC Controller2 named HDLC

controller2 connected to Iinput6/output6 of the switching matrix

C1/C0 : COMMAND

C1/C0 :

STATUS BITS

P0/1

: PROTOCOL BITS

Flag Monitoring

This bit is a status bit read by the microprocessor.

FM=1: HDLC Controller 2 is receiving a frame or HDLC Controller 2 has just received one flag.

FM is put to 0 by the microprocessor.

CRC

CRC stored in external memory

CRC = 1, the CRC is stored at the end of the frame in external memory.

CRC = 0, the CRC is not stored into external memory.

Command Bits

ABORT; if this command occurs during receiving a current frame, HDLC Controller stops the

reception, generates an interrupt and waits new command such as START or CONTINUE.

If this command occurs after receiving a frame, HDLC Controller generates an interrupt and

waits a new command such as START or CONTINUE.

START; Rx DMA Controller is now going to transfer first frame into buffer related to the initial

descriptor. The initial descriptor address is provided by the Initiate Block located in external

memory.

CONTINUE; Rx DMA Controller is now going to transfer next frame into buffer related to next

descriptor. The next descriptor address is provided by the previous descriptor from which the

related frame had been already received.

HALT; after receiving a frame, HDLC Controller stops the reception, generates an interrupt

and waits a new command such as START or CONTINUE.

Status Bits read by the microprocessor

ABORT; the received current frame has been aborted (seven “1” at least have been received)

or the microprocessor has written ABORT.

The HDLC Controller2 waits a new command such as START or CONTINUE

START; the microprocessor has written START.The HDLC Controller2 has not taken into ac-

count the command yet.

CONTINUE; RX DMA Controller is transferring frames

HALT; HDLC Controller2 stops the reception, generates an interrupt and waits a new com-

mand such as START or CONTINUE.

Transmission Mode

HDLC

Transparent Mode 1 (one byte per timeslot); the fill character defined in FCR Register is taken

into account.

Transparent Mode 2 (one byte per timeslot); the fill character defined in FCR Register is not

taken into account.

Reserved

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