STLC5466 datasheet(13/130 Pages) STMICROELECTRONICS

13 / 130 page

13/130

STLC5466

II - BLOCK DIAGRAM

The top level functionalities of Multi-HDLC appear

on the general block diagram.

There are:

– The switching matrix,

– The 2 time slot assigners,

– The 2 x 32 HDLC transmitters with associated

DMA controllers,

– The 2 x 32 HDLC receivers with associated

DMA controllers,

– The 16 Command/Indicate and Monitor Channel

transmitters belonging to the two General Com-

ponent Interfaces (GCI),

– The 16 Command/Indicate and Monitor Channel

receivers belonging to the two General Compo-

nent Interfaces (GCI),

– The Synchronous Dynamic Memory interface,

– The microprocessor interface including Write

FIFO and Fetch Memory,

– The bus arbitration,

– The clock selection and time synchronization

function,

– The interrupt controller,

– The watchdog

III - FUNCTIONAL DESCRIPTION

III.1 - The Switching Matrix N x 64 KBits/S

III.1.1 - Function Description

The matrix performs a non-blocking switch of 256

time slots from 8 Input Time Division Multiplex

(TDM) at 2 Mbit/s to 8 output Time Division Multi-

plex at 2 Mbit/s. A TDM at 2 Mbit/s consists of 32

Time Slots (TS) at 64 kbit/s. One Time Division

Multiplex at 4 Mbit/s can take place of two Time Di-

vision Multiplex at 2 Mbit/s. This TDM at 4 Mbit/s

is composed of 64 Time Slots (TS) at 64 kbit/s.

The matrix is designed to switch a 64 kbit/s chan-

nel (Variable delay mode) or an hyperchannel of

data (Sequence integrity mode). So, it will both

provide minimum throughput switching delay for

voice applications and time slot sequence integrity

for data applications on a per channel basis.

The requirements of the Sequence Integrity (n*64

kbit/s) mode are the following:

All the time slots of a given input frame must be put

out during a same output frame.

The time slots of an hyperchannel (concatenation

of TS in the same TDM) are not crossed together

at output in different frames.

In variable delay mode, the time slot is put out as

soon as possible. (The delay is two or three time

slots minimum between input and output).

For test facilities, any time slot of an Output TDM

(OTDM) can be internally looped back into the

same Input TDM number (ITDM) at the same time

slot number.

A Pseudo Random Sequence Generator and a

Pseudo Random Sequence Analyser are imple-

mented in the matrix. They allow the generation of

a sequence on a channel or on a hyperchannel, to

analyse it and verify its integrity after several

switching in the matrix or some passing of the se-

quence across different boards.

The Frame Signal (FS) synchronises ITDM and

OTDM but a programmable delay or advance can

be introduced separately on each ITDM and

OTDM (a half bit time, a bit time or two bit times).

An additional pin (PSS) permits the generation of

a programmable signal composed of 256 bits per

frame at a bit rate of 2048 kbit/s. The programma-

tion of this signal is performed thanks to PS bit of

Connection Memory.

An external pin (NDIS) asserts a high impedance

on all the TDM outputs of the matrix when active

(during the initialization of the board for example).

III.1.2 - Architecture of the Matrix

The matrix is essentially composed of buffer data

memories and a Connection Memory.

The received serial data is first converted to paral-

lel by a serial to parallel converter and stored con-

secutively in a 256 position Buffer Data Memory

(see Figure).

To satisfy the Sequence Integrity (n*64 kbit/s) re-

quirements, the data memory is built with an even

memory, an odd memory and an output memory.

Two consecutive frames are stored alternatively in

the odd and even memory. During the time an in-

put frame is stored, the one previously stored is

transferred into the output memory according to

the connection memory switching orders. A frame

later, the output memory is read and data is con-

verted to serial and transferred to the output TDM.

III.1.3 - Connection Function

Two types of connections are offered:

– unidirectional connection and

– bidirectional connection.

An unidirectional connection makes only the

switch of an input time slot through an output one

whereas a bidirectional connection establishes the

link in the other direction too. So a double connec-

tion can be achieved by a single command (see

Figure).

STLC5466 Arkusz danych(PDF) 13 Page - STMicroelectronics

STLC5466 Arkusz danych(HTML) 13 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL