STLC5466 datasheet(56/130 Pages) STMICROELECTRONICS

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STLC5466

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VI.27 - Initiate Block Address Register 1

IBAR1 (34)H

The Initiate Block Address (IBA1) is:

The 23 more significant bits define one of 8 Megawords. (One word comprises two bytes.)

The least significant bit defines one of two bytes when the microprocessor selects one byte.

Example: MHDLC device address inside

µP mapping = 100000H

Initiate Block for HDLC1 address inside

µP mapping = 110000H

IBAR1 value = (110000 - 100000)/256 = 100H

VI.28 - Interrupt Queue Size Register

IQSR(36)H

bit15

bit8

bit7

bit0

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

After reset (0000)H

A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the

external memory).The offset is zero (A0 to A7 =”0”).

This register concerns the first 32 HDLC Controller 1 named HDLC 1 connected to Din7/Dout7 of the

switching matrix. The Interrupt Queue is common for the first HDLC Controller1 and for the second HDLC

Controller 2. So this register concerns the location of the Interrupt Queue. The location of the Interrupt

Queue is found from the contents of this first IBAR Register 1 (34)H.

A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the

external memory in the MHDLC address space).The offset is zero (A0 to A7 =”0”).

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

bit15

bit8

bit7

bit0

TBFS

0000

000

HS2

HS1

HS0

MS2

MS1

MS0

CS1

CS0

After reset (0000)H

CS0/1 : Command/Indicate Interrupt Queue Size

These two bits define the size of Command/Indicate Interrupt Queue in external memory.

The location is IBA + 256 + HDLC Queue size + Monitor Channel Queue Size (see The Initiate

Block Address (IBA)).

MS0/2 : Monitor Channel Interrupt Queue Size

These three bits define the size of Monitor Channel Interrupt Queue in external memory.

The location is IBA + 256 + HDLC Queue size.

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