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STLC5466 Arkusz danych(PDF) 74 Page - STMicroelectronics |
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STLC5466 Arkusz danych(HTML) 74 Page - STMicroelectronics |
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74 / 130 page ![]() STLC5466 74/130 VII.3.2 - Bits written by the Tx DMAC only VII.3.3 - Transmit Buffer Each transmit buffer is defined by its transmit descriptor. The maximum size of the buffer is 2048 words (1 word=2 bytes) BOF : Beginning Of Frame BOF=1,the transmit buffer associated to this transmit descriptor contains the beginning of frame. The DMA Controller will store automatically the current descriptor address in the Initialization Block. BOF=0, the DMA Controller will not store the current descriptor address in the Initialization Block. EOF : End Of Frame EOF = 1,the transmit buffer associated to this transmit descriptor contains the end of frame. EOF = 0,the transmit buffer associated to this transmit descriptor does not contain the end of frame EOQ : End Of Queue EOQ = 1, the DMAC stops immediately its transmission, generates an interrupt (HDLC = 1 in IR) and waits a command from the HTCR (HDLC Transmit Command Register). EOQ = 0, the DMAC continues. CRCC : CRC Corrupted CRCC = 1,at the end of this frame the CRC will be corrupted by the Tx HDLC Controller. PRI : Priority Class 8 or 10 PRI = 1, if CSMA/CR is validated for this channel, the priority class is 8. PRI = 0, if CSMA/CR is validated for this channel the priority class is 10. (see Register CSMA) CFT : Frame correctly transmitted CFT = 1, the Frame has been correctly transmitted. CFT = 0, the Frame has not been correctly transmitted. ABT : Frame Transmitting Aborted ABT = 1, the frame has been aborted by the microprocessor during the transmission. ABT = 0, the microprocessor has not aborted the frame during the transmission. UND : Underrun UND = 1, the transmit FIFO has not been fed correctly during the transmission. UND = 0, the transmit FIFO has been fed correctly during the transmission. 15 0 TBA First Word to Transmit TBA + x; NBT is odd: x = NBT - 1 NBT is even: x = NBT - 2 Last Word to Transmit |
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