STLC5466 datasheet(69/130 Pages) STMICROELECTRONICS

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STLC5466

For information:

VI.43 - Initiate Block Address Register 2

IBAR2 (74)H

This register concerns the second 32 HDLC Controller 2 named HDLC 2 connected to input6/output6 of

the switching matrix. The Interrupt Queue is common for the first HDLC Controller and for the second

HDLC Controller 2. So this register doesn’t concern the location of the Interrupt Queue.The location of the

Interrupt Queue is found from the contents of the first IBAR1 register (34)H.

The Initiate Block Address (IBA2) is:

The 23 more significant bits define one of 8 Megawords. (One word comprises two bytes.)

The least significant bit defines one of two bytes when the microprocessor selects one byte.

Example: MHDLC device address inside

µP mapping = 100000H

Initiate Block for HDLC2 address inside

µP mapping = 310000H

IBAR2 value = (310000 - 100000)/256 = 2100H

LT2

LT1

LT0

NCAS latency

BL2

BL1

BL0

Burst Length

WT=0

Burst Length

WT=1

000

001

010

011

100

101

110

Full page

T,S,R :

These three bits define the SDRAM circuit organisation (1word=2bytes))

bit15

bit8

bit7

bit0

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

After reset (0000)H

A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the

external memory in the MHDLC address space).The offset is zero (A0 to A7 =”0”).

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

SDRAM circuit organization

(and shared RAM organization)

If refresh

(1Mx16) SDRAM circuit; shared RAM up to 4M words

2048 cycles / 32ms

(2Mx8) SDRAM circuit; shared RAM up to 8M words

4096 cycles / 64ms

(8Mx8) SDRAM circuit; shared RAM up to 8M words

4096 cycles / 64ms

(4Mx16) SDRAM circuit; shared RAM up to 8M words

4096 cycles / 64ms

Reserved

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