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STLC5466 Arkusz danych(PDF) 94 Page - STMicroelectronics |
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STLC5466 Arkusz danych(HTML) 94 Page - STMicroelectronics |
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94 / 130 page  STLC5466 94/130 Figure 1-12: Multi-HDLC connected to µP with multiplexed buses Figure 1-13: Multi-HDLC connected to µP with non multiplexed buses INTER FACE SDRAM INTER FACE BUS ARBITRATION ST9/10 Intel Motorola 8/16 bits Synchronous Dynamic RAM (organised by 16 bits) multiplex address/data bus address bus data bus MULTI-HDLC internal bus m P m P INTER FACE RAM INTER FACE BUS ARBITRATION Intel Motorola 8/16/32 bits address bus data bus address bus data bus MULTI-HDLC internal bus ST10 Synchronous Dynamic RAM (organised by 16 bits) m P m P |
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