STLC5466 datasheet(37/130 Pages) STMICROELECTRONICS

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STLC5466

VI.8 - Connection Memory Data Register

CMDR (0E)H

This 16 bit register is constituted by two 8 bit registers:

SOURCE REGISTER (SRCR) and CONTROL REGISTER (CTLR).

SOURCE REGISTER (SRCR)

This register defines the source when this source is located on an Input Time Division Multiplex ITDMp:

When D channels are multiplexed, see S0/S1 definition and tables here after.

M1/0

: Data Rate of TDM0/8;

These two bits indicate the data rate of height Time Division Multiplexes TDM0/7 relative to

DIN0/7 and DOUT0/7. The table below shows the different data rates with the clock frequency

defined by HCL bit (General Configuration Register).

N.B. The data rate of the Time Division Multiplex relative to DIN8, CB and Echo pins are at

2048 Kbit/s or1536 Kbit/s depending on M1/0 only.

SW0

: Switching at 32 Kbit/s for the TDM0 (DIN0/DOUT0)

SW0=1, DIN0 can receive 64 channels at 32 Kbit/s.

DIN2/DOUT2 are not available.

DIN2 is used to receive internally TDM0 (DIN0) after 4 bit shifting

DOUT2 is used to multiplex internally TDM2 and TDM4.

SW0=0, DIN0 receives 32 (or 24) channels at 64 Kbit/s or 64 channels at 64 Kbit/s depending

on DR04 bit and ClockA/B.

SW1

: Switching at 32 Kbit/s for the TDM1 (DIN1/DOUT1)

SW1=1, DIN1 can receive 64 channels at 32 Kbit/s.

DIN3/DOUT3 are not available.

DIN3 is used to receive internally TDM1(DIN1) after 4 bit shifting

DOUT3 is used to multiplex internally TDM3 and TDM5.

SW1=0, DIN1 receives 32 (or 24) channels at 64 Kbit/s or 64 channels at 64 Kbit/s depending

on DR04 bit and ClockA/B.

CONTROL REGISTER (CTLR)

SOURCE REGISTER (SRCR)

bit15

bit8

bit7

bit0

SCR

PRSA

OTSV LOOP

IM2

IM1

IM0

ITS 4 ITS 3

ITS 2

ITS 1

ITS 0

After reset (0000)H

ITS 0/4 : Input time slot 0/4 define ITSx with: 0

≤ x ≤ 31;

IM0/2

: Input Time Division Multiplex 0/2 define ITDMp with: 0

≤ p ≤ 7.

M1 M0

Data Rate of TDM0/7 in Kbit/s

CLOCKA/B signal frequency

HCL=0

HCL=1

2048 (or 4096 in accordance with DR0x4)

4096 KHz

8192 KHz

1536 (or 3072 in accordance with DR0x4)

3072 KHz

6144KHz

Reserved

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