STLC5466 datasheet(45/130 Pages) STMICROELECTRONICS

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STLC5466

VI.10 - Sequence Fault Counter Register

SFCR (12)H

When this register is read by the microprocessor, this register is reset (0000)H.

• NB. As the SFCR is reset after reading, a 8-bit microprocessor must read the LSB that will represent the

number of faults between 0 and 255. To avoid overflow escape notice, it is necessary to start counting

at FF00h, by writing this value in SFCR before launching PRSA. If there are more than FFh errors,

the SFCO interrupt bit (see interrupt register IR -38H address) will signal that the fault count register

has reached the value FFFFh (because of the number of faults exeeded 255).

VI.11 - Time Slot Assigner Address Register 1

TAAR1 (14)H

• N.B. After software reset (bit 2 of IDCR Register) or pin reset the automate above mentioned is working.

The automate is stopped when the microprocessor writes TAAR Register with HDI = 0.

VI.12 - Time Slot Assigner Data Register 1

TADR1 (16)H

bit15

bit8

bit7

bit0

F15

F14

F13

F12

F11

F10

After reset (0000)H

F0/15

: FAULT0/15

Number of faults detected by the Pseudo Random Sequence analyser if the analyser has been

validated and has recovered the receive sequence.

When the Fault Counter Register reaches (FFFF)H it stays at its maximum value.

bit15

bit8

bit7

bit0

TS4

TS3

TS2

TS1

TS0

READ

HDI

After reset (0100)H

READ

: READ MEMORY

READ = 1, Read Time slot Assigner Memory 1.

READ = 0, Write Time slot Assigner Memory 1.

TS0/4

: TIME SLOTS0/4

These five bits define one of 32 time slots in which a channel is set-up or not.

HDI

: HDLC1 INIT

HDI = 1, TSA1 Memory, Tx HDLC1, Tx DMA1, Rx HDLC1, Rx DMA1 and GCI controllers are

reset within 250 microseconds at the most. An automate writes data from Time slot Assigner

Data Register1 (TADR1) (except CH0/4 bits) into each TSA Memory location. If the microproc-

essor reads Time slot Assigner Memory 1 after HDLC INIT, CH0/4 bits of Time slot Assigner

Data Register are identical to TS0/4 bits of Time slot Assigner Address Register 1.

HDI = 0, Normal state.

bit15

bit8

bit7

bit0

V11

V10

CH4

CH3

CH2

CH1

CH0

After reset (0000)H

CH0/4

: CHANNEL0/4

These five bits define one of 32 channels associated to time slot defined by the previous Register

1(TAAR1).

V1/8

: VALIDATION

The logical channel CHx is constituted by each subchannel 1 to 8 and validated by V1/8 bit at 1 re-

spectively.

V1 to V8 are at “0’: the subchannels are ignored.

V1 corresponds to the first bit received during the current time slot.

V1 at 1: the first bit of the current time slot is taken into account in reception and in transmission the

first bit transmitted is taken into account.

V8 at 1: the last bit of the current time slot is taken into account in reception the last bit received and

in transmission the last bit transmitted in transmission.

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