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STLC5466 Arkusz danych(PDF) 76 Page - STMicroelectronics

Numer części STLC5466
Szczegółowy opis  64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED
PDF  130 Pages
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC5466 Arkusz danych(HTML) 76 Page - STMicroelectronics

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VII.5 - Receive Command / Indicate Interrupt
VII.5.1 - Receive Command / Indicate Interrupt when TSV = 0
Time Stamping not validated (bit of GCR Register)
This word is located in the Command/Indicate interrupt queue; IQSR Register indicates the size of this
interrupt queue located in the external memory.
CFR
: Correctly Frame Received
CFR =1, a receive frame is ended with a correct CRC. The end of the frame is located in the last
descriptor if several Descriptors.
bit15
bit8
bit7
bit 0
NS
Nu
S1
S0=0
G0
A2
A1
A0
Nu
Nu
C6
C5
C4
C3
C2
C1
NS
Nu
S1
S0=1
G0
A2
A1
A0
Nu
Nu
A
E
S1
S2
S3
S4
NS
: New Status.
Before writing the features of event in the external memory the Interrupt Controller reads the NS
bit:
if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the new primitive which has
been received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).
When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new
status. This location becomes free for the Interrupt Controller.
G0
: G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output.
G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output.
A2/0
: COMMAND/INDICATE Channel 0 to 7 being owned by GCI 0 or GCI 1
S1/0
: Primitive or 6 bit word or AIS received
C6/1
: New Primitive received twice consecutively. Case of S0=S1=0
A, E,
S1/S4
6 bits received twice consecutively. Case of S0=1 S1=0.
S1
S0
G0
Word stored in shared memory
0
0
0
Primitive C1/6 received from GCI Multiplex 0 corresponding to DIN4
0
0
1
Primitive C1/6 received from GCI Multiplex 1 corresponding to DIN5
0
1
0
A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI Multiplex 0 with-
out outgoing to DOUT4
0
1
1
A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 1 without outgo-
ing to DOUT5
1
0
0
AIS detected during more 30 ms from any input timeslot and switched to B1, B2 channels (16
bits) of the GCI Multiplex 0 (DOUT4) in transparent mode or not
1
0
1
AIS detected during more 30 ms from any input timeslot and switched to B1, B2 channels (16
bits) of the GCI Multiplex 1 (DOUT5) in transparent mode or not.
1
1
0
Reserved



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