STLC5466 datasheet(3/130 Pages) STMICROELECTRONICS

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STLC5466

III.3.3

Structure of the Treatment ...................................................................................................20

III.3.4

CI and Monitor Channel Configuration..................................................................................20

III.3.5

CI and Monitor Transmission/Reception Command .............................................................20

III.4

SCRAMBLER AND DESCRAMBLER...................................... ............................................20

III.5

CONNECTION BETWEEN “ISDN CHANNELS” AND GCI CHANNELS ..............................20

III.6

MICROPROCESSOR INTERFACE......................................... ............................................21

III.6.1

Description ...........................................................................................................................21

III.6.2

Buffer ...................................................................................................................................21

III.6.2.1

Write FIFO ........................................................................................................................21

III.6.2.2

Read Fetch Memory .........................................................................................................23

III.6.2.3

Definition of the Interface for the different microprocessors..............................................23

III.7

MEMORY INTERFACE ........................................................... ............................................23

III.7.1

Function Description ............................................................................................................23

III.7.2

Choice of memory versus microprocessor and capacity required ........................................23

III.7.3

Memory Cycle .......................................................................................................................23

III.7.4

Memories composed of different circuits ..............................................................................23

III.7.4.1

Memory obtained with 1M x16 SDRAM circuit..................................................................23

III.7.4.2

Memory obtained with 2M x 8 SDRAM circuit...................................................................23

III.7.4.3

Memory obtained with 8M x 8 SDRAM circuit...................................................................23

III.7.4.4

Memory obtained with 4M x 16 SDRAM circuit.................................................................24

III.8

BUS ARBITRATION ................................................................ ............................................24

III.9

CLOCKS .................................................................................. ............................................24

III.9.1

Clock Distribution Selection and Supervision .......................................................................24

III.9.2

VCXO Frequency Synchronization .......................................................................................24

III.10

INTERRUPT CONTROLLER................................................... ............................................25

III.10.1

Description ........................................................................................................... ................25

III.10.2

Operating Interrupts (INT0 Pin)........................................................................................ .....25

III.10.3

Time Base Interrupts (INT1 Pin) ........................................................................................ ...25

III.10.4

Emergency Interrupts (WDO Pin) ......................................................................................... 25

III.10.5

Interrupt Queues ..................................................................................................................25

III.11

WATCHDOG............................................................................ ............................................25

III.12

RESET ..................................................................................... ............................................25

III.13

BOUNDARY SCAN.................................................................. ............................................26

DC SPECIFICATIONS..........................................................................................................27

LIST OF REGISTERS ..........................................................................................................29

INTERNAL REGISTERS ......................................................................................................31

VI.1

IDENTIFICATION AND DYNAMIC COMMAND REGISTER... IDCR (00)H .........................31

VI.2

GENERAL CONFIGURATION REGISTER 1 .......................... GCR1 (02)H........................31

VI.3

INPUT MULTIPLEX CONFIGURATION REGISTER 0............ IMCR0 (04)H.......................33

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