STLC5466 datasheet(80/130 Pages) STMICROELECTRONICS

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STLC5466

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IX - FIGURES and TIMING

SEE FOLLOWING DOCUMENT

These FIGURES must be located in the following paragraphs:

Figure 1-1:

MHDLC Block diagram

in paragraph II

Figure 1-2:

Variable delay through the matrix with ITDM=1

in paragraph III 5.1

Figure 1-3:

Variable delay through the matrix with ITDM=0

in paragraph III 5.1

Figure 1-4:

Constant delay through the matrix with SI=1

in paragraph III 5.1

Figure 1-5:

Downstream switching at 32 kb/s

in paragraph III 1.7

Figure 1-6:

Upstream switching at 32 kb/s

in paragraph III 1.7

Figure 1-7:

Upstream and downstream switching at 16 Kbit/s

in paragraph III 1.8

Figure 1-8:

D,C/I and Monitor channel path

in paragraph III 3.3

Figure 1-9:

GCI channel to/from ISDN channel

in paragraph III 5

Figure 1-10:

From GCI channels to ISDN channels

in paragraph III 5

Figure 1-11:

From ISDN channels to GCI channels

in paragraph III 5

Figure 1-12:

Multi-HDLC connected to mP with multiplexed buses in paragraph III 6.2.3

Figure 1-13:

Multi-HDLC connected to mP with non multiplexed buses in paragraph III 6.2.3

Figure 1-14:

Microprocessor interface for INTEL 80C188

in paragraph III 6.2.3

Figure 1-15:

Microprocessor interface for INTEL 80C186

in paragraph III 6.2.3

Figure 1-16:

Microprocessor interface for MOROLA 68000

in paragraph III 6.2.3

Figure 1-17:

Microprocessor interface for MOROLA 68020

in paragraph III 6.2.3

Figure 1-18:

Microprocessor interface for ST9

in paragraph III 6.2.3

Figure 1-19:

Microprocessor interface for INTEL 386EX

in paragraph III 6.2.3

Figure 1-20:

Ex1; different clocks for Multi-HDLC and mP

in paragraph III 6.2.3

Figure 1-21:

Ex2; synchronous clock for Multi-HDLC and mP

in paragraph III 6.2.3

Figure 1-22:

4Mx16 SDRAM memory organisation

in paragraph III 7.4.1

Figure 1-23:

First example, 8Mx16 SDRAM memory organisation

in paragraph III 7.4.2

Figure 1-24:

Second example, 8Mx16 SDRAM memory organisation in paragraph III 7.4.3

Figure 1-25:

Third example, 8Mx16 SDRAM memory organisation in paragraph III 7.4.4

Figure 1-26:

Chain of n Multi-HDLC components

in paragraph III 8

Figure 1-27:

MHDLC clock generation

in paragraph III 9.1

Figure 1-28:

VCXO frequency synchronization

in paragraph III 9.2

Figure 1-29:

The three circular interrupt memories

in paragraph III 10.5

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