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STLC5466 Arkusz danych(PDF) 43 Page - STMicroelectronics |
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STLC5466 Arkusz danych(HTML) 43 Page - STMicroelectronics |
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43 / 130 page ![]() 43/130 STLC5466 – HCL=0, bit clock frequency is at 4 096 kHz For a TDM at 4 Mbit/s, each received bit is sampled at half bit-time (at 4 Mbit/s, bit-time=244ns). For a TDM at 2 Mbit/s, each received bit is sampled at 3/4 bit-time (at 2 Mbit/s, bit-time=488ns). • Remarks: OM0, bit5 of DSTR indicates either even TDM or odd TDM if TDM at 2 Mb/s. OM0, bit5 of DSTR indicates either even Output timeslot or odd Output timeslot if TDM at 4 Mb/s. IM0, bit5 of SRCR indicates either even TDM or odd TDM if TDM at 2 Mb/s. IM0, bit5 of SRCR indicates either even Input timeslot or odd Input timeslot if TDM at 4 Mb/s. |
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