STLC5466 datasheet(5/130 Pages) STMICROELECTRONICS

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STLC5466

VI.38

HDLC RECEIVE COMMAND REGISTER 2 ........................... HRCR2 (5A)H .....................65

VI.39

ADDRESS FIELD RECOGNITION ADDRESS REGISTER 2 AFRAR2 (5C)H ...................67

VI.40

ADDRESS FIELD RECOGNITION DATA REGISTER 2 ......... AFRDR2 (5E)H ...................67

VI.41

FILL CHARACTER REGISTER 2 ........................................... FCR2 (60)H ........................68

VI.42

SDRAM MODE REGISTER..................................................... SDRAMR (72)H ..................68

VI.43

INITIATE BLOCK ADDRESS REGISTER 2 ........................... IBAR2 (74)H .......................69

VI.44

TIMER REGISTER 2 ............................................................... TIMR2 (7C)H ......................70

VII

EXTERNAL REGISTERS.....................................................................................................71

VII.1

INITIALIZATION BLOCK IN EXTERNAL MEMORY (IBA1 AND IBA2)

VII.2

RECEIVE DESCRIPTOR.........................................................

VII.2.1

Bits written by the Microprocessor only ...............................................................................72

VII.2.2

Bits written by the Rx DMAC only ........................................................................................72

VII.2.3

Receive Buffer .....................................................................................................................73

VII.3

TRANSMIT DESCRIPTOR ...................................................... ............................................73

VII.3.1

Bits written by the Microprocessor only ...............................................................................73

VII.3.2

Bits written by the Tx DMAC only ........................................................................................74

VII.3.3

Transmit Buffer ....................................................................................................................74

VII.4

RECEIVE & TRANSMIT HDLC FRAME INTERRUPT ............ ............................................75

VII.5

RECEIVE COMMAND / INDICATE INTERRUPT.................... ............................................76

VII.5.1

Receive Command / Indicate Interrupt when TSV = 0 .........................................................76

VII.5.2

Receive Command / Indicate Interrupt when TSV = 1 .........................................................77

VII.6

RECEIVE MONITOR INTERRUPT.......................................... ............................................77

VII.6.1

Receive Monitor Interrupt when TSV = 0 .............................................................................77

VII.6.2

Receive Monitor Interrupt when TSV = 1 .............................................................................78

VIII

TQFP176 PACKAGE MECHANICAL DATA .......................................................................79

FIGURES AND TIMING........................................................................................................80

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