STLC5466 datasheet(55/130 Pages) STMICROELECTRONICS

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STLC5466

VI.25 - Transmit Monitor Interrupt Register

TMIR (30)H

When the microprocessor read this register, this register is reset (0000)H.

VI.26 - Memory Interface Configuration Register

MICR (32)H

bit15

TDM5

bit8

bit7

TDM4

bit0

MI71

MI61

MI51

MI41

MI31

MI21

MI11

MI01

MI70

MI60

MI50

MI40

MI30

MI20

MI10

MI00

After reset (0000)H

MIxy : Transmit Monitor Channel x Interrupt, Multiplex y with:

0 ≤ x ≤ 7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5

y = 0, GCI CHANNEL belongs to the multiplex TDM4 and y = 1 to TDM5.

MIxy = 1 when:

– a word has been transmitted and pre-acknowledged by the Transmit Monitor Channel xy (In

this case the Transmit Monitor Data Register (TMDR) is available to transmit a new word) or

– the message has been aborted by the remote receive Monitor Channel or

– the Timer has reached one millisecond (in accordance with TIV bit of TMAR) by IM3 bit of IMR.

When MIxy goes to “1”, the Interrupt MTX bit of IR is generated. Interrupt MTX can be masked.

bit15

bit8

bit7

bit0

P41

P40

P31

P30

P21

P20

P11

P10

REF

After reset (0000)H

REF

MEMORY REFRESH

REF=1, SDRAM REFRESH is validated

REF=0, SDRAM REFRESH is not validated

P1 E0/1

P2 E0/1

P3 E0/1

P4 E0/1

PRIORITY 1 for entity defined by E0/1

PRIORITY 2 for entity defined by E0/1

PRIORITY 3 for entity defined by E0/1

PRIORITY 4 for entity defined by E0/1

Entity definition:

PRIORITY 5 is the last priority for SDRAM Refresh if validated. SDRAM Refresh obtains

PRIORITY 0 (the first priority) automatically when the first half cycle is spend without access

to memory.

After reset (E400)H,

the Rx DMA Controller has the PRIORITY 1

the Microprocessor has the PRIORITY 2

the Tx DMA Controller has the PRIORITY 3

the Interrupt Controller has the PRIORITY 4

E 1

E 0

Entity

Rx DMA Controller

Microprocessor

Tx DMA Controller

Interrupt Controller

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