STLC5466 datasheet(21/130 Pages) STMICROELECTRONICS

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STLC5466

• in transmission: 16 ISDN channels (B1+B2+B*).

It is possible to switch the contents of B1, B2 and

D channels from 16 GCI channels in any 16 “ISDN

channels”, TDM side.

The contents of B1 and/or B2 can be scrambled or

not. If scrambled the number of the 32 timeslots

(TDM side) are different mandatory.

Receiving the contents of Monitor and Command

/ Indicate channels from 16 GCI channels. Primi-

tives and messages are stored automatically in

the external shared memory.

Transmitting “six bit word” (A, E, S1, S2, S3, S4)

to any 16 “ISDN channels” TDM side or not. See

SBV bit of General Configuration Register GCR

(02)H.

– Downstream. From ISDN channels to GCI chan-

nels.

• in reception: ISDN channel (B1+B2+B*)

• in transmission: GCI channel (B1+B2+MON+

D+C/I)

It is possible to switch the contents of B1, B2 and

D channels from 16 “ISDN channels”, TDM side in

16 GCI channels.

The contents of B1 and/or B2 can be descrambled

or not. If descrambled the 32 B1/B2 belong to GCI

channels mandatory.

Receiving six bit word (A, E, S1, S2, S3, S4) from

any 16 “ISDN channels”, TDM side. The 16 “six bit

word” are stored automatically in the external

shared memory.

Transmitting the contents of Monitor and Com-

mand / Indicate channels to 16 GCI channels. See

SBV bit of General Configuration Register GCR

(02)H.

– Alarm Indication Signal.

This detection concerns 16 hyperchannels. One

hyperchannel comprises 16 bits (B1 and B2 only).

The Alarm Indications for the 16 hyperchannels

are stored automatically in the external shared

memory. See AISD bit of Switching Matrix Config-

uration Register SMCR (0C)H.

III.6 - Microprocessor Interface

III.6.1 - Description

The Multi-HDLC circuit can be controlled by sever-

al types of microprocessors (ST9/10, Intel/Motoro-

la 8 or 16 data bits interfaces) such as:

– ST9/10 family

– INTEL 80C188 8 bits

– INTEL 80C186 16 bits

– INTEL 386EX 16 bits

– MOTOROLA 68000 16 bits

– MOTOROLA 68020 32 bits

Table 14: Microprocessor Interface Selection

During the initialization of the Multi-HDLC circuit,

the microprocessor interface is informed of the

type of microprocessor that is connected by polar-

isation of three external pins MOD 0/2.

Three chip Select (CS0/2) pins are provided. CS0

will select the internal registers and CS1 the exter-

nal memory. CS2 can be used to select the exter-

nal memory in INTEL 386EX application only (see

pin 41 definition).

III.6.2 - Buffer

A Buffer is located in the microprocessor interface.

It is used whatever microprocessor selected

thanks to MOD0/2 pins. It allows to reduce the

shared memory access cycles for the microproc-

essor.

This Buffer consists of one Write FIFO and one

Read Fetch Memory (see Figure).

III.6.2.1 - Write FIFO

When the microprocessor delivers the address

word named Ax to write data named [Ax] in the

shared memory in fact it writes data [Ax] and ad-

dress word Ax in the Write FIFO (8 words). If Ax is

in Fetch Memory, [Ax] is removed in Fetch Memo-

ry.

There is no wait time for the microprocessor if the

Write FIFO is not full entirely.

MOD2

MOD1

MOD0

Microprocessor

80C188

80C186

68000

68020

ST9

ST10 A/D multiplexed

ST10 A/D Not multiplexed

386EX

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