ST25R200 datasheet(16/88 Pages) STMICROELECTRONICS

16 / 88 page

Table 2. SPI signal lines

Name

Signal

Signal level

Description

BSS

Digital input

CMOS

SPI enable (active low)

MOSI

Digital input

CMOS

Serial data input

SCLK

Digital input

CMOS

Clock for serial communication

MISO

Digital output with tristate

CMOS

Serial data output

MISO output is usually in tristate. It is only driven when output data is available. Due to this the MOSI and the

MISO can be externally shorted to create a bidirectional signal.

During the time the MISO output is in tristate, it is possible to switch on a 10 kΩ pull down by activating option bits

miso_pd1 and miso_pd2.

Figure 8. SPI data signals with a host

MOSI

MISO

MOSI

ST25R

MOSI

MISO

I/O MCU

ST25R

MCU

The following addressing scheme is used:

•

Bit 7 indicates the direction of the operation (0-Write / 1-Read)

•

95 addressable registers (0x00 - 0x5E)

•

64 command codes (0x60 - 0x7F and 0xE0 - 0xFF)

•

FIFO access (0x5F)

•

Test/OTP registers access (0xFC)

For specific details on ST25R200 registers and commands, refer to the Section 5.14: Registers and

Section 5.15: Direct commands.

Table 3. SPI operation modes

MODE

MODE pattern (com. bits)

Related data

R/W B6 B5 B4 B3 B2 B1 B0

A6 A5 A4 A3 A2 A1 A0

Data byte (or more bytes in case of auto-incrementing) A<6,0>=0x5E

max

A6 A5 A4 A3 A2 A1 A0

Data byte (or more bytes in case of auto-incrementing) A<6,0>=0x5E

max

Commands

C4 C3 C2 C1 C0 -

Test

Enable access to test registers

FIFO write

One or more bytes of FIFO data

FIFO read

One or more bytes of FIFO data

ST25R200

Application information

DS13658 - Rev 2

page 16/88

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