P83CE558EBBSLASHYYY datasheet(46/72 Pages) PHILIPS

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Philips Semiconductors

Preliminary specification

P83CE558/P80CE558/P89CE558

Single-chip 8-bit microcontroller

1996 Aug 06

6.14

Reset Circuitry

The reset input pin RSTIN is connected to a Schmitt trigger for noise

reduction (see Figure 46). Is the HF-oscillator selected a Reset is

accomplished by holding the RSTIN pin HIGH for at least 2 machine

cycles (24 system clock periods). Is the PLL-oscillator selected the

RSTIN-pulse must have a width of 1

µs at least, independent of the

32 kHz-oscillator is running or not (see PLL description). The CPU

responds by executing an internal reset. The RSTOUT pin

represents the signal resetting the CPU and can be used to reset

peripheral devices.

The RSTOUT level also could be high due to a Watchdog timer

overflow.

The length of the output pulse from T3 is 3 machine cycles. A pulse

of such short duration is necessary in order to recover from a

processor or system fault as fast as possible.

During Reset, ALE and PSEN output a HIGH level. In order to

perform a correct reset, this level must not be affected by external

elements.

A Reset leaves the internal registers as shown in Table 5.

The internal RAM is not affected by Reset. At power-on, the RAM

content is indeterminate.

6.15

Power-on Reset

An automatic Reset can be obtained by switching on VDD, if the

RSTIN pin is connected to VDD via a capacitor, as shown in

Figure 47.

Is the HF oscillator selected the VDD rise time must not exceed 10

ms and the capacitor should be at least 2.2

µF. The decrease of the

RSTIN pin voltage depends on the capacitor and the internal resistor

RRST. That voltage must remain above the lower threshold for at

minimum the HF-oscillator start-up time plus 2 machine cycles. Is

the PLL-oscillator selected a 0.1

µF capacitor is sufficient to obtain

an automatic reset.

8xCE558

VDD

RST

RRST

HF-Osc.:

2.2

µF

VDD

Figure 46. On-chip Reset Configuration

RRST

RSTIN

Schmitt

Trigger

On-chip

resistor

Overflow

timer T3

Figure 47. Power-on Reset

MUX

RSTOUT

Internal

Reset

SELXTAL1

PLL-Osc.: 0.1

µF

PLL

OSC

Capacitor for

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