P83CE558EBBSLASHYYY datasheet(33/72 Pages) PHILIPS

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Philips Semiconductors

Preliminary specification

P83CE558/P80CE558/P89CE558

Single-chip 8-bit microcontroller

1996 Aug 06

When SIO1 is in a master mode serial clock frequency is

determined by the clock rate bits CR2, CR1 and CR0. The various

bit rates are shown in Table 25.

Table 25.

Selection of I2C-bus bit rate

BIT RATE (kHz) at fCLK

CR2

CR1

CR0

12MHz

16MHz

66.7

3.75

100

–

200 1

266.7 1

7.5

300 1

400 1

–

NOTE:

1. These bit rates are for “fast-mode” I2C bus applications and cannot be used for bit rates up to 100 kbit/sec.

The data shown in Table 25 do not apply to SIO1 in a slave mode. In

the slave modes, SIO1 will automatically synchronize with any clock

frequency up to 400kHz.

Serial status register S1STA

S1STA is a read only register.

The contents of the status register may be used as a vector to a

service routine. This optimizes the response time of the software

and consequently that of the I2C-bus.

Figure 31. Serial status (S1STA) register.

S1STA (D9H)

SC4

SC3

SC2

SC1

SC0

Table 26.

Description of S1STA bits

BIT

FUNCTION

S1STA.7 to 3

5-bit status code

S1STA.2 to 0

These bits are held LOW (for service routine vector increment 8)

The following is a list of the status codes:

Table 27.

MST/TRX mode

S1STA VALUE

DESCRIPTION

08H

A START condition has been transmitted

10H

A repeated START condition has been transmitted

18H

SLA and W have been transmitted, ACK has been received

20H

SLA and W have been transmitted, ACK received

28H

DATA and S1DAT has been transmitted, ACK received

30H

DATA and S1DAT has been transmitted, ACK received

38H

Arbitration lost in SLA, R/W or DATA

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