P83CE558EBBSLASHYYY datasheet(27/72 Pages) PHILIPS

27 / 72 page

Philips Semiconductors

Preliminary specification

P83CE558/P80CE558/P89CE558

Single-chip 8-bit microcontroller

1996 Aug 06

Figure 25. Set enable register (STE).

STE (EEH)

TG47

TG46

SP45

SP44

SP43

SP42

SP41

SP40

Table 20.

Description of STE bits

SYMBOL

BIT

FUNCTION

TG47

STE.7

If “1” then P4.7 is reset on the next toggle, if LOW P4.7 is set on the next toggle

TG46

STE.6

If “1” then P4.6 is reset on the next toggle, if LOW P4.6 is set on the next toggle

SP45

STE.5

If “1” then P4.5 is set on a match between CM0 and Timer T2

SP44

STE.4

If “1” then P4.4 is set on a match between CM0 and Timer T2

SP43

STE.3

If “1” then P4.3 is set on a match between CM0 and Timer T2

SP42

STE.2

If “1” then P4.2 is set on a match between CM0 and Timer T2

SP41

STE.1

If “1” then P4.1 is set on a match between CM0 and Timer T2

SP40

STE.0

If “1” then P4.0 is set on a match between CM0 and Timer T2

Figure 26. Reset/Toggle enable register (RTE).

RTE (EFH)

TP47

TP46

RP45

RP44

RP43

RP42

RP41

RP40

Table 21.

Description of RTE bits

SYMBOL

BIT

FUNCTION

TP47

RTE.7

If “1” then P4.7 toggles on a match between CM2 and Timer T2

TP46

RTE.6

If “1” then P4.6 toggles on a match between CM2 and Timer T2

RP45

RTE.5

If “1” then P4.5 toggles on a match between CM1 and Timer T2

RP44

RTE.4

If “1” then P4.4 toggles on a match between CM1 and Timer T2

RP43

RTE.3

If “1” then P4.3 toggles on a match between CM1 and Timer T2

RP42

RTE.2

If “1” then P4.2 toggles on a match between CM1 and Timer T2

RP41

RTE.1

If “1” then P4.1 toggles on a match between CM1 and Timer T2

RP40

RTE.0

If “1” then P4.0 toggles on a match between CM1 and Timer T2

For more information concerning the TM2CON, CTCON, TM2IR and

the STE/RTE registers see IC20 handbook, chapter “80C51 family

hardware description”.

Port 4 can be read and written by software without affecting the

toggle, set and reset signals. At a byte overflow of the least

significant byte, or at a 16-bit overflow of the timer/counter, an

interrupt sharing the same interrupt vector is requested. Either one

or both of these overflows can be programmed to request an

interrupt.

All interrupt flags must be reset by software.

P83CE558EBB/YYY Arkusz danych(PDF) 27 Page - NXP Semiconductors

P83CE558EBB/YYY Arkusz danych(HTML) 27 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Arkusz danych Pobierz

Link URL