P83CE558EBBSLASHYYY datasheet(32/72 Pages) PHILIPS

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Philips Semiconductors

Preliminary specification

P83CE558/P80CE558/P89CE558

Single-chip 8-bit microcontroller

1996 Aug 06

The Control Register, S1CON:

The CPU can read from and write to this 8-bit, directly addressable

SFR. Two bits are affected by the SIO1 hardware: the SI bit is set

when a serial interrupt is requested, and the STO bit is cleared when

a STOP condition is present on the I2C bus. The STO bit is also

cleared when ENS1 = 0.

Figure 30. Serial control (S1CON) register.

S1CON (D8H)

CR2

ENS1

STA

STO

CR1

CR0

Table 24.

Description of S1CON bits

SYMBOL

BIT

FUNCTION

CR2

S1CON.7

Clock rate bit 2, see Table 25.

ENS1

S1CON.6

ENS1 = 0:

Serial I/O

disabled and reset. SDA and SCL outputs are high-Z.

ENS1 = 1:

Serial I/O

enabled.

STA

S1CON.5

START flag. When this bit is set in slave mode, the hardware checks the I2C bus and generates a START

condition if the bus is free or after the bus becomes free. If the device operates in master mode it will

generate a repeated START condition.

STO

S1CON.4

STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on

the I2C bus clears this bit. This bit may also be set in slave mode in order to recover from an error

condition. In this case no STOP condition is generated to the I2C bus, but the hardware releases the SDA

and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware.

S1CON.3

Serial Interrupt flag. This flag is set, and an interrupt request is generated, after any of the following events

occur:

– A START condition is generated in master mode.

– The own slave address has been received during AA = 1.

– The general call address has been received while S1ADR.0 and AA = 1.

– A data byte has been received or transmitted in master mode (even if arbitration is lost).

– A data byte has been received or transmitted as selected slave.

– A STOP or START condition is received as selected slave receiver or transmitter.

While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must be reset by software.

S1CON.2

Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following

conditions:

– Own slave address is received.

– General call address is received (S1ADR.0 = 1).

– A data byte is received, while the device is programmed to be a master receiver.

– A data byte is received. while the device is a selected slave receiver.

When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own

address or general call address is received.

CR1

CR0

S1CON.1

S1CON.0

Clock rate bits 1 and 0, see Table 25.

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