P83CE558EBBSLASHYYY datasheet(52/72 Pages) PHILIPS

52 / 72 page

Philips Semiconductors

Preliminary specification

P83CE558/P80CE558/P89CE558

Single-chip 8-bit microcontroller

1996 Aug 06

FLASH EEPROM

8.1

General

• 32 Kbytes electrically erasable internal program memory with

Block-and Page-Erase option (”Flash Memory”).

• Internal fixed boot ROM.

• Up to 32 Kbytes external program memory in combination with the

internal FEEPROM (EA=1).

• Up to 64 Kbytes external program memory if the internal program

memory is switched off (EA=0).

The FEEPROM can be read and written byte-wise. Full Erase, Block

Erase, and Page erase will erase 32 Kbytes, 256 bytes and 32 bytes

respectively. In-circuit programming and out-of-circuit programming

is possible. On-chip erase and write timing generation and on chip

high voltage generation contribute to a user friendly interface.

8.2

Features

• Read:

byte-wise

• Write:

byte-wise within 2.5 ms.

(previously erased by a page, block or full erase).

• Erase:

Page Erase (32 bytes) within 5 ms.

Block Erase (256 bytes) within 5 ms.

Full Erase (32 Kbytes) within 5 ms.

Erased bytes contain FFH.

• Endurance:

100 erase and write cycles each byte at Tamb = 22°C

• Retention:

10 years

• Out-of-circuit programming:

Parallel programming with 87C51 compatible hardware

Interface to programmer.

• In-circuit programming:

Serial programming via RS232 interface under boot ROM

program control. Auto baud rate selection.

Intel Hex Object file Format.

The user program can call routines in the boot ROM for

erase, write and verify of the FEEPROM.

• High programming voltage generation: on chip

• Zero point on-chip oscillator and timer to generate the write and

erase time durations.

• Programmable security for the code in the FEEPROM to prevent

software piracy. The Security Byte is located in the highest

address (7FFFH) of the FEEPROM.

• Supply voltage monitoring circuit on-chip to prevent loss of

information in the FEEPROM during power-on and power-off.

8.3

Memory Map

Figure 48 shows the memory map of the user program memory and

the boot ROM. They are located in the same program address

space. Two bits UBS1 and UBS0 of the FEEPROM control special

function register FMCON select between the two memory blocks.

User program memory selection

If UBS1 and UBS0 are both 0, then the user program memory is

mapped into the 64 K program memory space and the boot ROM

cannot be selected. This is the situation after a reset when PSEN

and ALE have not been pulled down during reset. Program

execution starts at 0000H in the internal FEEPROM or in the

external program memory dependent on the level of EA during

reset.

Boot ROM selection

After a reset program execution starts in the boot ROM when during

reset PSEN and EA are pulled down while ALE stay high. The boot

ROM size is 1 Kbyte. Besides the serial in-circuit programming

routine the boot ROM contains the routines for erase, write and

verify of the FEEPROM, which can be called by the user program

(LCALL to the address space between 63 K and 64 K).

Switching between user program memory and boot ROM

Switching between user program memory (internal or external) and

boot ROM is possible if UBS1 and UBS0 are 0,1. Then in the

program memory address space between 0 and 63k the user

program memory is selected and in the memory space between 63

K and 64 K the boot ROM is selected.

To switch from user program memory to boot ROM first UBS0 must

be set (UBS1 stay 0) and a jump or call instruction to a location >63

K must be executed.

At the moment of crossing the 63 K address border by a return

instruction the switching from boot ROM to user memory (internal or

external) is performed. After crossing the 63 K address border UBS1

and UBS0 are cleared and the total 64 K memory space is mapped

as user program memory. By clearing UBS1 and UBS0, no special

requirements to the user program are necessary to do that after a

read or erase or write routine.

A small restriction for memory switching is that no memory switching

is allowed from or to the address space between 63 K and 64 K of

the user program memory because the UBS bits must stay 0 in this

range. This restriction can be avoided if the memory switching is

always done by a subroutine in the address range between 0 and

63 K.

Description

The user program code in the FEEPROM is executed as in the

standard 80C51 microcontroller. Erase and write cycles in the

FEEPROM are always performed under control of the boot program

in the boot ROM in the address space between 63 K and 64 K.

Address and data parameters are passed via DPTR and

accumulator A respectively. During an erase or write cycle in the

FEEPROM no other access or program execution in the FEEPROM

is possible. All interrupts must be disabled when the user program

calls a user routine in the boot ROM.

The boot routine for serial programming takes care of addressing,

data transfer, verify, high voltage control, error message and return

to the user program memory. It also contains the serial

communication routine.

The FEEPROM control register FMCON is a special function

ROM switching.

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