P83CE558EBBSLASHYYY datasheet(36/72 Pages) PHILIPS

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Philips Semiconductors

Preliminary specification

P83CE558/P80CE558/P89CE558

Single-chip 8-bit microcontroller

1996 Aug 06

6.10

Interrupt System

External events and the real-time-driven on-chip peripherals require

service by the CPU asynchronously to the execution of any

particular section of code. To tie the asynchronous activities of these

functions to normal program execution a multiple-source,

two-priority-level, nested interrupt system is provided. Interrupt

response time in a single-interrupt system is in the range from

2.25

µs to 6.75µs when using a 16MHz crystal. The latency time

depends on the sequence of instructions executed directly after an

interrupt request.

The P8xCE558 acknowledges interrupt requests from 15 sources as

follows (see Figure 34):

• INT0 and INT1 external interrupts

• Timer 0 and Timer 1 internal timer/counter interrupts

• Timer 2 internal timer/counter byte and/or 16-bit overflow, 3

compare and 4 capture interrupts (or 4 additional external

interrupts) 1

• UART serial I/O port receive/transmit interrupt

• I2C-bus interface serial I/O interrupt

• ADC autoscan completion interrupt

• ‘Seconds’ timer interrupt SEC (ored with INT1).

For details about seconds timer interrupts, please refer to chapter

6.13.4.

The External Interrupts INT0 and INT1 can each be either

level-activated or transition-activated, depending on bits IT0 and IT1

in register TCON. The flags that actually generate these interrupts

are bits IE0 and IE1 in TCON. When an external interrupt is

generated, the corresponding request flag is cleared by the

hardware when the service routine is vectored to only if the interrupt

was transition-activated. If the interrupt was level-activated then the

interrupt request flag remains set until the external interrupt pin INTx

goes high. Consequently the external source has to hold the request

active until the requested interrupt is actually generated. Then it has

to deactivate the request before the interrupt service routine is

completed, or else another interrupt will be generated. As these

external interrupts are active LOW a “wire-ORing” of several

interrupt sources to one input pin allows expansion.

The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1,

which are set by a rollover in their respective timer/counter register

(except for Timer 0 in Mode 3 of the serial interface). When a Timer

interrupt is generated, the flag that generated it is cleared by the

on-chip hardware when the service routine is vectored to.

The eight Timer/Counter T2 Interrupt sources are: 4 capture

Interrupts (1), 3 compare interrupts and an overflow interrupt. The

appropriate interrupt request flags must be cleared by software.

The UART Serial Port Interrupt is generated by the logical OR of RI

and TI. Neither of these flags is cleared by hardware. The service

routine will normally have to determine whether it was RI or TI that

generated the interrupt, and the bit will have to be cleared by

software.

The I2C Interrupt is generated by bit SI in register S1CON. This flag

has to be cleared by software.

The ADC Interrupt is generated by bit ADINT, which is set when of

all selected analog inputs to be scanned, the conversion is finished.

ADINT must be cleared by software. It cannot be set by software.

The ’Seconds’ timer Interrupt is generated by bit SECINT in register

PLLCON. This flag has to be cleared by software. Note that the

’Seconds’ timer can only be used with the

32 kHz PLL oscillator.

All of the bits that generate interrupts can be set or cleared by

software, with the same result as though it had been set or cleared

by hardware (except the ADC interrupt request flag ADINT, which

cannot be set by software). That is, interrupts can be generated or

pending interrupts can be cancelled in software.

The Interrupts X0, T0, X1, T1, SEC, S0 and S1 are capable to

terminate the Idle Mode.

Interrupt Enable Registers

Each interrupt source can be individually enabled or disabled by

setting or clearing a bit in the interrupt enable special function

registers IEN0 and IEN1. All interrupt sources can also be globally

disabled by clearing bit EA in IEN0. The interrupt enable registers

are described in Figures 34 and 36.

Interrupt Priority Structure

Each interrupt source can be assigned one of two priority levels.

Interrupt priority levels are defined by the interrupt priority special

function registers IP0 and IP1. IP0 and IP1 are described in Figures

37 and 38.

Interrupt priority levels are as follows:

“0”—low priority

“1”—high priority

A low priority interrupt may be interrupted by a high priority interrupt.

A high priority interrupt cannot be interrupted by any other interrupt

source. If two requests of different priority occur simultaneously, the

high priority level request is serviced. If requests of the same priority

are received simultaneously, an internal polling sequence

determines which request is serviced. Thus, within each priority

level, there is a second priority structure determined by the polling

sequence. This second priority structure is shown in Table 37.

Interrupt Handling

The interrupt sources are sampled at S5P2 of every machine cycle.

The samples are polled during the following machine cycle. If one of

the flags was in a set condition at S5P2 of the previous machine

cycle, the polling cycle will find it and the interrupt system will

generate an LCALL to the appropriate service routine, provided this

hardware- generated LCALL is not blocked by any of the following

conditions:

1. An interrupt of higher or equal priority level is already in

progress.

2. The current machine cycle is not the final cycle in the execution

of the instruction in progress. (No interrupt request will be

serviced until the instruction in progress is completed.)

3. The instruction in progress is RETI or any access to the interrupt

priority or interrupt enable registers. (No interrupt will be serviced

after RETI or after a read or write to IP0, IP1, IE0, or IE1 until at

least one other instruction has been subsequently executed.)

NOTE:

1. If a capture register is unused and it’s contents is of no interest, then the corresponding input pin CTnI/P1.n (n: 0...3) may be used as a

(configurable) positive and/or negative edge triggered additional external interrupt input (INT2, INT3, INT4, INT5).

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