IXP45X datasheet(70/148 Pages) INTEL

70 / 148 page

Package Information

August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

Table 18.

Serial Peripheral Port Interface

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

SSP_SCLK

SSP_SCLK is the serial bit clock used to control the timing of a transfer. SSP_SCLK can be generated

internally (Master mode) as defined by a control register bit internal to the IXP45X/IXP46X network

processors.

SSP_SFRM

SSP_SFRM is the serial frame indicator that indicates the beginning and the end of a serialized data

word. The SSP_SFRM can be generated internally (Master mode) or taken from an external source

(Slave mode) as defined by a control register bit internal to the IXP45X/IXP46X network processors.

This signal may be active low or active high depending upon the mode of operation.

Please refer to the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s

Manual for additional details.

SSP_TXD

SSP_TXD is the Transmit data (serial data out) serialized data line. Sample length is a function of the

selected serial data sample size.

SSP_RXD

SSP_RXD is the Receive data (serial data in) serialized data line. Sample length is a function of the

selected serial data sample size.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

SSP_EXTCLK

SSP_EXTCLK is an external clock which can be selected to replace the internal 3.6864 MHz clock. The

SSP_EXTCLK input is selected by setting various internal registers to appropriate values.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

Table 19.

I2C Interface

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Softwar

Enables

Type†

Description

I2C_SDA

VOD

I/O/

The receive and transmit data/address line used to communicate between various master and slave I2C

interfaces. A pull up resistor is required on this interface. Please refer to the I2C specification.

I2C_SCL

VOD

I/O/

The master and slave clock line used to communicate between various master and slave I2C interfaces. A

pull up resistor is required on this interface.

Please refer to the I2C specification.

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

IXP45X Arkusz danych(PDF) 70 Page - Intel Corporation

IXP45X Arkusz danych(HTML) 70 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL