IXP45X datasheet(53/148 Pages) INTEL

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August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

Table 14.

UTOPIA Level 2/MII_A/ SMII Interface (Sheet 1 of 7)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

UTP_OP_CLK /

ETHA_TXCLK

ZVI

UTOPIA Mode of Operation:

UTOPIA Transmit clock input. Also known as UTP_TX_CLK. This signal is used to synchronize all

UTOPIA transmit outputs to the rising edge of the UTP_OP_CLK.

MII Mode of Operation:

Externally supplied transmit clock.

• 25 MHz for 100 Mbps operation

• 2.5 MHz for 10 Mbps operation

SMII Mode of Operation:

Not Used.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor.

UTP_OP_FCO

TRI

UTOPIA flow control output signal. Also known as the TXENB_N signal.

Used to inform the selected PHY that data is being transmitted to the PHY. Placing the PHY’s

address on the UTP_OP_ADDR — and bringing UTP_OP_FCO to logic 1, during the current clock —

followed by the UTP_OP_FCO going to a logic 0, on the next clock cycle, selects which PHY is

active in MPHY mode.

In SPHY configurations, UTP_OP_FCO is used to inform the PHY that the processor is ready to

send data.

This signal must be tied to Vcc with an external 10-KΩ resistor.

UTP_OP_SOC

TRI

Start of Cell. Also known as TX_SOC.

Active high signal is asserted when UTP_OP_DATA contains the first valid byte of a transmitted

cell.

This signal must be tied to Vss with an external 10-KΩ resistor.

UTP_OP_DATA[3:0] /

ETHA_TXDATA[3:0]

TRI

UTOPIA Mode of Operation:

UTOPIA output data. Also known as UTP_TX_DATA. Used to send data from the processor to an

ATM UTOPIA Level 2-compliant PHY.

MII Mode of Operation:

Transmit data bus to PHY, asserted synchronously with respect to ETHA_TXCLK. This MAC

interface does not contain hardware hashing capabilities local to the interface. In this mode of

operation the pins represented by this interface are ETHA_TXDATA3:0].

SMII mode of operation:

Not used.

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

††

For information on selecting the desired interface, see the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual.

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