IXP45X datasheet(51/148 Pages) INTEL

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August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

HSS_RXDATA0

Receive data input. Can be sampled on the rising or falling edge of the receive clock.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the HSS soft

fuse (refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product

Line of Network Processors Developer’s Manual) and is not being used in a system design, this

interface/signal is not required for any connection.

HSS_RXCLK0

I/O

The High-Speed Serial (HSS) receive clock signal can be configured as an input or an output. The

clock can be from 512 KHz to 8.192 MHz. Used to sample the received data. Configured as an

input upon reset.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor.

Table 13.

High-Speed, Serial Interface 1 (Sheet 1 of 2)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

HSS_TXFRAME1

I/O

The High-Speed Serial (HSS) transmit frame signal can be configured as an input or an output to

allow an external source to be synchronized with the transmitted data. Often known as a Frame

Sync signal. Configured as an input upon reset.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the HSS soft

fuse (refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product

Line of Network Processors Developer’s Manual) and is not being used in a system design, this

interface/signal is not required for any connection.

HSS_TXDATA1

VOD

Transmit data out. Open Drain output.

When this interface/signal is enabled and either used or unused in a system design, it should be

pulled high with a 10-KΩ resistor to VCCP. When this interface is disabled via the HSS soft fuse

(refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of

Network Processors Developer’s Manual) and is not being used in a system design, this interface/

signal is not required for any connection.

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

Table 12.

High-Speed, Serial Interface 0 (Sheet 2 of 2)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

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