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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

Document Number: 306261-004US

The MCU supports two banks of DDR SDRAM. The MCU has support for unbuffered

DDRI 266 only.

Table 4 illustrates the supported DDR SDRAM configurations for the IXP45X/IXP46X

network processors. The 128/256/512-Mbit, 1-Gbit DDRI SDRAM devices comprise four

internal leaves. The MCU controls the leaf selects within 128/256/512-Mbit, 1-Gbit

DDRI SDRAM by toggling DDRI_BA[0] and DDRI_BA[1].

The two DDR SDRAM chip enables (DDRI_CS[1:0]#) support a DDRI SDRAM memory

subsystem consisting of two banks. The base address for the two contiguous banks are

programmed in the DDR SDRAM Base Register (SDBR) and must be aligned to a 32-

Mbyte boundary. The size of each DDR SDRAM bank is programmed with the DDR

SDRAM boundary registers (SBR0 and SBR1).

The memory controller is a 32-bit only interface. If a x16 memory chip is used, a

minimum of two memory chips would be required to facilitate the 32-bit interface

required by the IXP45X/IXP46X network processors. If ECC is required, additional

memories would need to be added. For more information on DDRI SDRAM support and

configuration see the Intel® IXP45X and Intel® IXP46X Product Line of Network

Processors Developer’s Manual.

The memory controller internally interfaces to the North AHB, South AHB, and Memory

Port Interface with independent interfaces. This architecture allows DDRI SDRAM

transfers to be interleaved and pipelined to achieve maximum possible efficiency.

The maximum burst size supported to the DDRI SDRAM interface is eight 32-bit words.

This burst size allows the best efficiency/fairness performance between peripheral

accesses from the North AHB, the South AHB, and the MPI.

Table 4.

Supported DDRI Memory Configurations

DDRI SDRAM

Technology

DDRI SDRAM

Arrangement

# Banks

Address Size

Leaf Select

Total

Memory

Size1

Page

Size2

Row

Col

DDRI_BA[1]

DDRI_BA[0]

128 Mbit

16M x 8

I_AD[26]

I_AD[25]

64 Mbyte

128 Mbyte

8M x 16

I_AD[25]

I_AD[24]

32 Mbyte

64 Mbyte

256 Mbit

32M x 8

I_AD[27]

I_AD[26]

128 Mbyte

256 Mbyte

16M x 16

I_AD[26]

I_AD[25]

64 Mbyte

128 Mbyte

512 Mbit

64M x 8

I_AD[28]

I_AD[27]

256 Mbyte

512 Mbyte

32M x 16

I_AD[27]

I_AD[26]

128 Mbyte

256 Mbyte

1 Gbit

128M x 8

I_AD[29]

I_AD[28]

512 Mbyte

21 Gbyte

64M x 16

I_AD[28]

I_AD[27]

256 Mbyte

512 Mbyte

Notes:

Table indicates 32-bit-wide memory subsystem sizes

Table indicates 32-bit-wide memory page sizes

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