IXP45X datasheet(37/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

August 2006

Datasheet

Document Number: 306261-004US

Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

3.2.12

Debug Unit

The debug unit is accessed through the JTAG port. The industry-standard, IEEE 1149.1

JTAG port consists of a test access port (TAP) controller, boundary-scan register,

instruction and data registers, and dedicated signals TDI, TDO, TCK, TMS, and TRST#.

The debug unit — when used with debugger application code running on a host system

outside of the Intel XScale® processor — allows a program, running on the Intel

XScale® processor, to be debugged. It allows the debugger application code or a debug

exception to stop program execution and redirect execution to a debug-handling

routine.

Debug exceptions are instruction breakpoint, data breakpoint, software breakpoint,

external debug breakpoint, exception vector trap, and trace buffer full breakpoint. Once

execution has stopped, the debugger application code can examine or modify the Intel

XScale® processor’s state, coprocessor state, or memory. The debugger application

code can then restart program execution.

The debug unit has two hardware-instruction, break point registers; two hardware,

data-breakpoint registers; and a hardware, data-breakpoint control register. The

second data-breakpoint register can be alternatively used as a mask register for the

first data-breakpoint register.

A 256-entry trace buffer provides the ability to capture control flow messages or

addresses. A JTAG instruction (LDIC) can be used to download a debug handler via the

JTAG port to the mini-instruction cache (the I-cache has a 2-Kbyte, mini-instruction

cache, like the mini-data cache, that is used only to hold a debug handler).

4.0

Package Information

This section contains information on the following topics:

• “Package Description” which includes “Package Drawings”, “Package Markings”,

and “Part Numbers”

• “Functional Signal Definitions” on page 43

• “Signal-Pin Descriptions” on page 77

• “Package Thermal Specifications” on page 102

4.1

Package Description

The IXP45X/IXP46X network processors are built using a 544-ball, plastic ball grid

array (PBGA) package with a drop-in heat spreader (H).

For all extended temperature products and the 667-MHz speed option of the

commercial temperature product, a 10-mm-high, thermal-adhesive-based heat sink

will be required. The heat sink does not force the addition of any surface area to the

board design.

4.1.1

Package Drawings

The package is shown in Figure 5 and Figure 6.

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