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IXP45X Arkusz danych(PDF) 74 Page - Intel Corporation |
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IXP45X Arkusz danych(HTML) 74 Page - Intel Corporation |
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74 / 148 page ![]() Package Information August 2006 Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet 74 Document Number: 306261-004US JTG_TDO Z VO/Z VO / Z VO / Z TRI Output data for the IEEE 1149.1 JTAG interface. JTG_TRST_N H VI/H VI VI I Used to reset the IEEE 1149.1 JTAG interface. Important: The JTG_TRST_N signal must be asserted (driven low) during power-up, otherwise the TAP controller will not be initialized properly and the processor may be locked. When the JTAG interface is not being used, the signal must be pulled low using a 10-KΩ resistor. JTG_TCK Z VI VI VI I Used as the clock for the IEEE 1149.1 JTAG interface. Table 24. System Interface (Sheet 1 of 2) Name Power on Reset† Reset† Normal After Reset Until Software Enables Possible Configur ations After Software Enables Type† Description BYPASS_CLK Z VI VI VI I Used for test purposes only. Must be pulled high using a 10-KΩ resistor for normal operation. SCANTESTMODE_N VI/H VI/H VI / H VI / H I Used for test purposes only. Must be pulled high using a 10-KΩ resistor for normal operation. RESET_IN_N VI/H VI/H VI / H VI / H I Used as a reset input to the device when PWRON_RESET_N is in an inactive state and once power up conditions are met. Power up conditions include the following: — Power supplies reaching a safe stable condition and — The PLL achieving a locked state PWRON_RESET_N VI/H VI/H V I/ H VI / H I Signal used at power up to reset all internal logic to a known state after the PLL has achieved a locked state. The PWRON_RESET_N signal is a 3.3-V signal. HIGHZ_N VI / H VI / H VI / H VI / H I Used for test purposes only. Must be pulled high using a 10-KΩ resistor for normal operation. Note: This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor, see Table 1 on page 13. † For a legend of the Type codes, see Table 8 on page 43. Table 23. JTAG Interface (Sheet 2 of 2) Name Power on Reset† Reset† Normal After Reset Until Software Enables Possible Configur ations After Software Enables Type† Description Note: This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor, see Table 1 on page 13. † For a legend of the Type codes, see Table 8 on page 43. |
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