IXP45X datasheet(62/148 Pages) INTEL

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August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

ETHB_COL

MII Mode of Operation:

Asserted by the PHY when a collision is detected by the PHY. This MAC interface does not contain

hardware hashing capabilities local to the interface.

• When NPE B is configured in MII mode of operation and the signal is not being used, it

should be pulled low through a 10-KΩ resistor.

SMII Mode of Operation:

Not used.

• When NPE B is configured in SMII mode of operation, this signal must be pulled high with a

10-KΩ resistor.

When this interface is disabled via the NPE-B Ethernet 0 and/or the NPE Ethernet 1-3 soft fuse

(refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line

of Network Processors Developer’s Manual) and is not being used in a system design, this

interface/signal is not required for any connection.

ETHB_CRS/

SMII_SYNC/

SMII_TXSYNC

VI / VO

I/O

MII Mode of Operation:

Asserted by the PHY when the transmit medium or receive medium is active. De-asserted when

both the transmit and receive medium are idle. Remains asserted throughout the duration of a

collision condition. PHY asserts CRS asynchronously and de-asserts synchronously, with respect

to ETHB_RXCLK. This MAC interface does not contain hardware hashing capabilities local to the

interface.

SMII Mode of Operation:

In SMII Mode of Operation, this signal is an output that creates a synchronous pulse once every

10 SMII_CLK reference clocks to signal the start of the next 10 bits of data to be transmitted/

received. SMII_CLK Reference clock operates at 125MHz.

In Source Synchronous mode of operation, a synchronous pulse output created once every 10

SMII_TXCLK clocks to signal the start of the next 10 bits of data to be transmitted. SMII_TXCLK

operates at 125MHz.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the NPE-B

Ethernet 0 and/or the NPE Ethernet 1-3 soft fuse (refer to Expansion Bus Controller chapter of

the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual)

and is not being used in a system design, this interface/signal is not required for any connection.

In MII mode of operation, this signal is a valid input. In SMII mode of operation this signal is a

valid output.

Table 15.

MII/SMII Interfaces (Sheet 4 of 7)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

††

Please refer to Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired

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