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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

Document Number: 306261-004US

This PMU is for the Intel XScale® processor only. An additional PMU is supplied for

monitoring of internal bus performance.

• JTAG debug unit that uses hardware break points and 256-entry trace history

buffer (for flow-change messages) to debug programs

3.2.1

Super Pipeline

The super pipeline is composed of integer, multiply-accumulate (MAC), and memory

pipes.

The integer pipe has seven stages:

• Branch Target Buffer (BTB)/Fetch 1

•Fetch 2

•Decode

• Register File/Shift

•ALU Execute

• State Execute

• Integer Writeback

The memory pipe has eight stages:

• The first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute)

. . . then finishes with the following memory stages

• Data Cache 1

• Data Cache 2

• Data Cache Writeback

Figure 4.

Intel XScale® Technology Block Diagram

A9568-01

Multiply

Accumulate

Execution

Core

Interrupt

Request

Instruction

FIQ

Coprocessor Interface

IRQ

Data

Address

Data

System

Management

Debug/

PMU

JTAG

South

AHB

Bus

Data Cache

32 Kb

Mini-Data Cache

2 Kb

Instruction Cache

32 Kb

Branch Target Cache

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