IXP45X datasheet(10/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

Document Number: 306261-004US

— Full-speed capable

— Embedded transceiver

— 16 endpoints

• USB 2.0 host controller

— Low-speed and full-speed capable

— Embedded transceiver

— EHCI Compliant

— Separate interface from USB 1.1 device controller

• DDRI-266 SDRAM interface

— Internally multi-ported Memory Controller Unit (Three Internal Ports)

— 32-bit data

—13-bit address

— 133.32 MHz (which is 4 * OSC_IN input pin)

— Supports 128/256/512/1,024-Mbit technologies

— Unbuffered DDRI SDRAM support only

— Up to eight open pages simultaneously maintained

— Support for 32 Mbyte, minimum; 1 Gbyte, maximum

— User-enabled, single-bit error correction/multi-bit error detection ECC support

(ECC not supported on Intel® IXP455 Network Processor)

• Expansion interface

— Master/Target interface

—25-bit address

— 32-bit data

— Eight programmable outbound chip selects

— One inbound chip select

— Four request/grant pairs

— Outbound transfers (IXP45X/IXP46X network processors are the master to

external target devices)

— Inbound transfers (IXP45X/IXP46X network processors are a target to external

masters)

— Bus tri-state for sideband transfers (External masters accesses to external

target device)

— Outbound transfer support

• Supports Intel/Motorola* microprocessors

• Multiplexed-style bus cycles

• Simplex-style bus cycles

• Support for Texas Instruments* DSPs using HPI*-8 bus cycles

• Support for Texas Instruments DSPs using HPI-16 bus cycles

• Synchronous flash support

• Flow through ZBT SRAM burst support

• Up to 80-MHz operation at 40 pF load

• Supports even/odd-parity generation and checking in all extended modes and

in some legacy modes (Intel and Motorola style bus cycles)

— Inbound transfer support

• Single transfer or burst transfers

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