IXP45X datasheet(49/148 Pages) INTEL

49 / 148 page

Package Information

August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

PCI_REQ_N[0]

VI / VO

I/O

PCI arbitration request:

• When configured as an input (PCI arbiter enabled), the internal PCI arbiter will allow an agent

to request the PCI bus.

• When configured as an output (PCI arbiter disabled), the pin will be used to request access to

the PCI bus from an external arbiter.

When this interface/signal is enabled and is not being used in a system design, the interface/signal

should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse

(refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of

Network Processors Developer’s Manual) and is not being used in a system design, this interface/

signal is not required for any connection.

PCI_GNT_N[3:1]

PCI arbitration grant: Generated by the internal PCI arbiter to allow an agent to claim control of the

PCI bus.

PCI_GNT_N[0]

VI / VO

I/O

PCI arbitration grant:

• When configured as an output (PCI arbiter enabled), the internal PCI arbiter to allow an agent

to claim control of the PCI bus.

• When configured as an input (PCI arbiter disabled), the pin will be used to claim access of the

PCI bus from an external arbiter.

When this interface/signal is enabled and is not being used in a system design, the interface/signal

should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse

(refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of

Network Processors Developer’s Manual) and is not being used in a system design, this interface/

signal is not required for any connection.

PCI_INTA_N

VOD

O/D

PCI interrupt: Used to request an interrupt.

When this interface/signal is enabled and is not being used in a system design, the interface/signal

should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse

(refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of

Network Processors Developer’s Manual) and is not being used in a system design, this interface/

signal is not required for any connection.

PCI_CLKIN

PCI Clock: Clock provides timing for all transactions on PCI. All PCI signals — except INTA#, INTB#,

INTC#, and INTD# — are sampled on the rising edge of CLK and timing parameters are defined

with respect to this edge. The PCI clock rate can operate at up to 66 MHz.

When this interface/signal is enabled and is not being used in a system design, the interface/signal

should be pulled high with a 10-KΩ resistor.

Table 11.

PCI Controller (Sheet 4 of 4)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

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