IXP45X datasheet(61/148 Pages) INTEL

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August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

ETHB_RXDATA[3:0] /

SMII_RXDATA[0] /

SMII_RXDATA[1] /

SMII_RXDATA[2] /

SMII_RXDATA[3]

ZVI

MII Mode of Operation:

Receive data bus from PHY, data sampled synchronously with respect to ETHB_RXCLK. This MAC

interface does not contain hardware hashing capabilities local to the interface.

SMII Mode of Operation:

Each SMII_RXDATA line is a separate physical port

ETHB_RXDATA[3] is multiplexed with SMII_RXDATA[3],

ETHB_RXDATA[2] is multiplexed with SMII_RXDATA[2],

ETHB_RXDATA[1] is multiplexed with SMII_RXDATA[1],

ETHB_RXDATA[0] is multiplexed with SMII_RXDATA[0]

The data on these signal are received synchronously with respect to the rising edge of SMII_CLK

when operating as an SMII interface and synchronously with respect to the rising edge of

SMII_RXCLK when operating as a Source Synchronous SMII interface

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the NPE-B

Ethernet 0 and/or the NPE Ethernet 1-3 soft fuse (refer to Expansion Bus Controller chapter of

the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual)

and is not being used in a system design, this interface/signal is not required for any connection.

One special configuration exists for the board designer. When NPE B is configured in SMII mode

of operation and a subset of the four SMII ports are utilized (i.e. All four are enabled but only two

are being connected). The unused inputs must be tied high with a 10-KΩ resistor.

ETHB_RXDV /

SMII_RXSYNC

ZVI

MII Mode of Operation:

Receive data valid, used to inform the MII interface that the Ethernet PHY is sending data. This

MAC interface does not contain hardware hashing capabilities local to the interface.

SMII Mode of Operation:

In Source Synchronous mode of operation, this signal is an input from a synchronous pulse

created once every 10 SMII_RXCLK reference clocks to signal the start of the next 10 bits of data

to be received. SMII_RXCLK Reference clock operates at 125MHz.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the NPE-B

Ethernet 0 and/or the NPE Ethernet 1-3 soft fuse (refer to Expansion Bus Controller chapter of

the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual)

and is not being used in a system design, this interface/signal is not required for any connection.

Table 15.

MII/SMII Interfaces (Sheet 3 of 7)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

††

Please refer to Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired

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