IXP45X datasheet(73/148 Pages) INTEL

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Package Information

August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

Table 22.

GPIO Interface

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

GPIO[12:0]

I/O

General purpose Input/Output pins. May be configured as an input or an output. As an input, each signal

may be configured a processor interrupt. Default after reset is to be configured as inputs. Some GPIO may

serve as an optional alternate function.

Refer to Section 3.1.12, “GPIO” on page 27, for additional details on alternate function mapping.

Should be pulled high using a 10-KΩ resistor when not being utilized in the system.

GPIO[13]

I/O

General purpose input/output pins. May be configured as an input or an output. Default after reset is to be

configured as inputs. Some GPIO may serve as an optional alternate function.

Refer to Section 3.1.12, “GPIO” on page 27, for additional details on alternate function mapping.

Should be pulled high using a 10-KΩ resistor when not being utilized in the system.

GPIO[14]

I/O

Can be configured the same as GPIO Pin 13 or as a clock output. Configuration as an output clock can be

set at various speeds of up to 33 MHz with various duty cycles. Configured as an input, upon reset. Some

GPIO may serve as an optional alternate function.

Refer to Section 3.1.12, “GPIO” on page 27, for additional details on alternate function mapping.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

GPIO[15]

clkout /

I/O

Can be configured the same as GPIO Pin 13 or as a clock output. Configuration as an output clock can be

set at various speeds of up to 33 MHz with various duty cycles. Configured as an output, upon reset. Can

be used to clock the expansion interface, after reset. Some GPIO may serve as an optional alternate

function.

Refer to Section 3.1.12, “GPIO” on page 27, for additional details on alternate function mapping.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system. The interface should

be set to an input in the not used configuration.

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

Table 23.

JTAG Interface (Sheet 1 of 2)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

JTG_TMS

VI / H

VI/H

Test mode select for the IEEE 1149.1 JTAG interface.

JTG_TDI

VI /H

VI/H

Input data for the IEEE 1149.1 JTAG interface.

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

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