IXP45X datasheet(57/148 Pages) INTEL

57 / 148 page

Package Information

August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

UTP_IP_DATA[4] /

ETHA_RXDV

ZVI

UTOPIA Mode of Operation:

UTOPIA input data. Also known as RX_DATA.

Used by to the processor to receive data from an ATM UTOPIA Level 2-compliant PHY.

MII Mode of Operation:

Receive data valid, used to inform the MII interface that the Ethernet PHY is sending data.

This MAC does not contains hardware hashing capabilities local to the interface.

SMII mode of operation:

Not used.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the UTOPIA

and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel®

IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual) and is not

being used in a system design, this interface/signal is not required for any connection.

UTP_IP_DATA[5] /

ETHA_COL

ZVI

UTOPIA Mode of Operation:

UTOPIA input data. Also known as RX_DATA.

Used by the processor to receive data from an ATM UTOPIA Level 2-compliant PHY.

• When NPE A is configured in UTOPIA mode of operation and the signal is not being used, it

should be pulled high through a 10-KΩ resistor.

MII Mode of Operation:

Asserted by the PHY when a collision is detected by the PHY.

• When NPE A is configured in MII mode of operation and the signal is not being used, it should

be pulled low through a 10-KΩ resistor.

SMII Mode of Operation:

Not used.

• When NPE A is configured in SMII mode of operation, this signal must be pulled high through

a 10-KΩ resistor.

When this interface is disabled via the UTOPIA and/ or the NPE-A Ethernet soft fuse (refer to the

Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of Network

Processors Developer’s Manual) and is not being used in a system design, this interface/signal is

not required for any connection.

Table 14.

UTOPIA Level 2/MII_A/ SMII Interface (Sheet 5 of 7)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

††

For information on selecting the desired interface, see the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual.

IXP45X Arkusz danych(PDF) 57 Page - Intel Corporation

IXP45X Arkusz danych(HTML) 57 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL