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IXP45X Arkusz danych(PDF) 72 Page - Intel Corporation |
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IXP45X Arkusz danych(HTML) 72 Page - Intel Corporation |
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72 / 148 page ![]() Package Information August 2006 Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet 72 Document Number: 306261-004US USB_HPEN Z Z VO VO O Enable to the external VBUS power source USB_HPWR Z Z VI VI I External VBUS power is in over current condition When this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the USB Device soft fuse (refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual) and is not being used in a system design, this interface/signal is not required for any connection. Table 21. Oscillator Interface Name Power on Reset† Reset† Normal After Reset Until Software Enables Possible Configur ations After Software Enables Type† Description OSC_IN n/a VI VI VI I 33.33-MHz, sinusoidal input signal. Can be driven by an oscillator. OSC_OUT n/a VO VO VO O 33.33-MHz, sinusoidal output signal. Left disconnected when being driven by an oscillator. Note: This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor, see Table 1 on page 13. † For a legend of the Type codes, see Table 8 on page 43. Table 20. USB Host/Device Interfaces (Sheet 2 of 2) Name Power on Reset† Reset† Normal After Reset Until Software Enables Possible Configur ations After Software Enables Type† Description Note: This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor, see Table 1 on page 13. † For a legend of the Type codes, see Table 8 on page 43. †† Please refer to the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Hardware Design Guidelines for additional board design details. |
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