IXP45X datasheet(20/148 Pages) INTEL

20 / 148 page

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

Document Number: 306261-004US

3.1.2.1

North AHB

The North AHB is a 133.32-MHz (which is 4 * OSC_IN input pin), 32-bit bus that can be

mastered by the NPE A, NPE B, or NPE C. The targets of the North AHB can be the DDRI

SDRAM or the AHB/AHB bridge. The AHB/AHB bridge allows the NPEs to access the

peripherals and internal targets on the South AHB.

Data transfers by the NPEs on the North AHB to the South AHB are targeted

predominately to the queue manager. Transfers to the AHB/AHB bridge may be

“posted” — when writing — or “split” — when reading.

When a transaction is “posted,” a master on the North AHB requests a write to a

peripheral on the South AHB. If the AHB/AHB Bridge has a free FIFO location, the write

request will be transferred from the master on the North AHB to the AHB/AHB bridge.

The AHB/AHB bridge will complete the write on the South AHB, when it can obtain

access to the peripheral on the South AHB. The North AHB is released to complete

another transaction.

When a transaction is “split,” a master on the North AHB requests a read of a peripheral

on the South AHB. If the AHB/AHB bridge has a free FIFO location, the read request will

be transferred from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB

bridge will complete the read on the South AHB, when it can obtain access to the

peripheral on the South AHB.

Once the AHB/AHB bridge has obtained the read information from the peripheral on the

South AHB, the AHB/AHB bridge notifies the arbiter, on the North AHB, that the AHB/

AHB bridge has the data for the master that requested the “split” transfer. The master

on the North AHB — that requested the split transfer — will arbitrate for the North AHB

and transfer the read data from the AHB/AHB bridge. The North AHB is released to

complete another transaction while the North AHB master — that requested the “split”

transfer — waits for the data to arrive.

These “posting” and “splitting” transfers allow control of the North AHB to be given to

another master on the North AHB — enabling the North AHB to achieve maximum

efficiency. Transfers to the AHB/AHB bridge are considered to be small and infrequent,

relative to the traffic passed between the NPEs and the DDRI SDRAM on the North AHB.

When multiple masters arbitrate for the North AHB, the masters are awarded access to

the bus in a round-robin fashion. Each transaction can be no longer than an eight-word

burst. This implementation promotes fairness within the system.

3.1.2.2

South AHB

The South AHB is a 133.32-MHz (which is 4 * OSC_IN input pin), 32-bit bus that can be

mastered by the Intel XScale® processor, PCI controller, Expansion Bus Interface, USB

Host Controller, and the AHB/AHB bridge. The targets of the South AHB Bus can be the

DDRI SDRAM, PCI Controller, Queue Manager, Expansion Bus, or the AHB/APB bridge.

As a special case, the Intel XScale® Processor is the only master which can access the

Cryptography Unit (target).

Accesses across the APB/AHB bridge allows interfacing to peripherals attached to the

APB. The Expansion bus and PCI controller can be configured to support split transfers.

Arbitration on the South AHB are round-robin. Each transaction can be no longer than

an eight-word burst. This implementation promotes fairness within the system.

IXP45X Arkusz danych(PDF) 20 Page - Intel Corporation

IXP45X Arkusz danych(HTML) 20 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL