AD4884BBCZ datasheet(65/116 Pages) AD

65 / 116 page

Data Sheet

AD4884

DIGITAL INTERFACE

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Rev. 0 | 65 of 116

Self Clock Mode

In LVDS data interface mode, it is possible to disable the DCO+ChX

and DCO−ChX echo clock output (see the Echo Clock Mode sec-

tion) by setting LVDS_SELF_CLK_MODE = 1 in the ADC Data

Interface Configuration B register (see the ADC Data Interface

Configuration B Register section, Address 0x16). This setting puts

the device in self clock mode disabling the DCO+ChX and DCO−ChX

output driver, with the benefit of saving interface power as well

as reducing the number of LVDS pairs required to interface with

the host controller. In this mode, the DCO+ChX and DCO−ChX pins

can be left disconnected, therefore, in single-lane configurations,

a minimum of two LVDS pairs (CLK+ChX and CLK−ChX, DA+ChX

and DA−ChX) are required to connect to each AD4884 instance.

The interface connectivity can further be simplified by sharing the

interface clock (CLK+ChX and CLK−ChX) between multiple AD4884

instances.

Figure 112. Continuous Conversion Timing, LVDS Data Interface, Single Data Lane, Self Clock Mode

Figure 113. Continuous Conversion Timing, LVDS Data Interface, Dual Data Lane, Self Clock Mode

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